1. Field of the Invention
This invention relates to a novel construction of an integrated circuit package and a method for fabricating the same. In particular, the invention relates to forming an improved package particularly suited for multiple-unit three-dimensional stacking. This improved package is fabricated by attaching a lead frame to an integrated circuit package in a manner that results in improved thermal transfer of heat from within the integrated circuit package and provides additional electrical conductors useful with addressing and communicating multiple package modules.
2. Discussion of the Related Technology
Packaging techniques for integrated circuits have been developed in the past in an attempt to satisfy demands for miniaturization in the semiconductor industry. Improved methods for miniaturization of integrated circuits enabling the integration of millions of transistor circuit elements into single integrated silicon embodied circuits, or chips, have resulted in increased emphasis on methods to package these circuits in space efficient, yet reliable and mass producible packages.
Integrated circuits are created from a silicon wafer using various etching, doping and depositing steps that are well know in the art of fabricating integrated circuit devices. A silicon wafer may be comprised of a number of integrated circuit dies that each represent a single integrated circuit chip. Ultimately, the chip may be packaged by using a lead frame connected to the electrical circuit connection pads of the chip, supported in and passing through the plastic encasement around the chip to be further connected to a variety of external pin-out or mounting and interconnection schemes.
The lead frame extends beyond the encapsulating package and is used to connect the electrical circuits contained within the chip to the electronic system connection means, such as a printed circuit board. Typical molded case integrated circuit packages include, for example, M-Dip (Dual-In-Line-Plastic), SIP (Single-In-Line-Plastic), PLCC (Plastic Leaded Chip Carrier), SOJ (Small Outline J-leaded) and TSOP (Thin Small Outline Package) molded case packages.
Operating electronic circuits generate heat. The amount of heat generated depends on the circuit complexity, speed and power requirements. Thus, the requirement for adequate heat dissipation increases with greater circuit complexity (number of transistors) and operating speeds. This heat must be dissipated from within the integrated circuit package by thermal convection or conduction cooling. Heat may be removed through thermal conduction from the package and lead frame by, for example, convective air flow around the package, conduction through the lead frame into the printed circuit board, and/or conduction through the package into a system heat sink.
In an attempt to configure electronic systems in ever smaller packages, new methods and apparatus comprising three dimensional stacked integrated circuit packages have been developed as more fully described in U.S. patent application Ser. Nos. 07/561,417 and 07/884,066, filed Aug. 1, 1990 and May 15, 1992, respectively, both having the common assignee of the present invention and incorporated herein by reference for all purposes. Such multiple package modules pose an even greater need for heat dissipation and further typically require more circuit pin-outs or leads to address and communicate between the individual packages and external circuitry.
A method and apparatus to efficiently remove heat from the integrated circuit die encapsulated within the integrated circuit package is needed that is both reliable and easy to mass produce. When the thermal conduction from the integrated circuit package is improved, the junction temperatures of the transistors of the integrated circuit chip within the package are lowered, thus, improving the reliability of the integrated circuit package. In addition, an improved thermally conductive individual package may be used in a higher thermal density application without degradation in overall performance or reliability.
An example of a hermetically sealed ceramic integrated circuit heat dissipating package having improved thermal dissipation characteristics is more fully described in co-pending U.S. patent application Ser. No. 07/905,587, filed Jun. 26, 1992, having the common assignee of the present invention and incorporated herein by reference for all purposes. An example of a fabrication method and apparatus for lead-on-chip integrated circuits having improved thermal dissipation characteristics is more fully described in co-pending U.S. patent application Ser. No. 07/746,268, filed Aug. 15, 1991 and Patent Cooperative Treaty International application No. PCT/US92/06778, both having the common assignee of the present invention and incorporated herein by reference for all purposes. There are, however, integrated circuit packages in commercial production such as, for example, the TSOP type whose thermal transfer characteristics could be improved upon after manufacture by modifying such packages in accordance with the present invention, thus allowing greater integrated circuit packaging densities and improved reliability.